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| FUJITSU SEMICONDUCTOR DATA SHEET DS07-03108-2E Processor Digital Signal Processor CMOS 16-bit Fixed-point DSP MB86330 s DESCRIPTION The MB86330 is a 16-bit fixed-point DSP (Digital Signal Processor) that is based on Fujitsu-specific Dual-MAC architecture, and can implement product addition operations and double transfer at a high rate and under low power consumption. The DSP supports a set of instructions optimum for digital signal processing in communications applications such as handy phones. The MB86330 consists of a core section and a peripheral section. For detailed specifications of the core section, see MB86330DSP Core Section Specifications. s FEATURES * Fixed-point operations Multiplication: 16 bits x 16 bits 31 bits Addition: 40 bits + 40 bits 40 bits Product addition: 40 bits 16 bits x 16 bits 40 bits Maximum operation speed: 100 MIPS at 3.3 V * Memory configuration Data RAM: Two sectors that can be accessed concurrently An external RAM (ERAM) is supported. Memory mapped I/O system characterized by allocation of I/O devices in the memory space Instruction RAM: 48 Kwords x 16 bits Table RAM: 16 Kwords x 16 bits (Continued) s PACKAGE 256-pin Ceramic PGA (PGA-256C-A03) MB86330 (Continued) * Addressing Two independent address units Eight general-purpose registers Addressing function that can update a register Circular addressing Two address update registers * Supply voltage: 3.3 V (single type of supply voltage) * Ceramic package: PGA-256 2 MB86330 s PIN ASSIGNMENT (Top view) 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 54 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 73 2 53 120 179 180 181 182 183 184 185 186 187 188 189 190 191 192 137 74 3 52 119 178 229 230 231 232 233 234 235 236 237 238 239 240 193 138 75 4 51 118 177 228 50 117 176 227 49 116 175 226 252 48 115 174 225 47 114 173 224 251 46 113 172 223 45 112 171 222 250 44 111 170 221 43 110 169 220 249 42 109 168 219 41 108 167 218 40 107 166 217 216 215 39 106 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 88 17 38 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 18 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 253 248 214 213 254 247 212 211 255 246 210 209 256 Extra index pin 245 208 207 241 194 139 76 5 195 140 77 6 196 141 78 7 197 142 79 8 242 198 143 80 9 199 144 81 10 243 200 145 82 11 201 146 83 12 244 202 147 84 13 203 148 85 14 204 149 86 15 206 205 150 87 16 (PGA-256C-A03) 3 MB86330 Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O O I O O O I O O O I O O O O O O -- -- O O I O O O O O -- O I/O I/O I/O -- Pin name PAO27 ICAD0 PAO30 IRO0 IRO3 ICAD1 IRO8 IRO10 IRO14 ICAD3 IRO17 IRO20 IRO23 IRO26 IRO28 IRO30 N.C. N.C. PAGE1 XERD WMD0 EA1 EA4 EA5 EA9 EA11 N.C. EA15 ED2 ED6 ED8 N.C. Pin no. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I/O I/O -- I/O I/O I/O -- I/O -- O O I I -- -- -- -- I I O O -- -- I I O I I O O O O I Pin name ED13 N.C. ICDT12 ICDT10 ICDT6 N.C. ICDT3 N.C. AINT6 AINT5 INT4 SCZC N.C. N.C. N.C. N.C. F0 MOD0 AINT2 AINT1 N.C. N.C. SMCK SMEN PDXED SYI1 SCI1 SDO0 SDO1 PAO0 PAO4 ICCN Pin no. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 I/O O O O O O O O O O O O O O O I O O O O -- O -- -- -- O O I O -- O O O Pin name PAO7 PAO10 ST2 PAO13 PAO15 FF PAO21 PAO23 PAO24 PAO28 PAO31 IRO1 IRO4 IRO6 ICAD2 IRO13 IRO16 IRO18 IRO21 N.C. IRO27 N.C. N.C. N.C. BTACT XEWR WMD1 EA2 N.C. EA7 EA10 EA14 Pin no. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O I/O O I I I -- -- I I I -- I -- -- -- -- I I I I O O Pin name EDI ED3 N.C. ED10 ED12 ED15 ICDT13 ICDT11 ICDT9 ICDT5 ICDT2 AINT7 INT6 INT5 INT3 N.C. N.C. MCLK BREAK MOD2 N.C. INT1 N.C. N.C. N.C. VS SY10 SDI1 SYO0 SYO1 XMONI PAO3 N.C.: Pin not connected (Continued) 4 MB86330 (Continued) Pin no. 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 I/O O O O O O O O O O O -- O O O O O O O O O -- -- I O -- O O -- O I/O I/O I/O Pin name PAO6 PAO8 PAO11 ST1 PAO14 PAO17 PAO20 PAO22 PAO25 PAO29 N.C. IRO2 IRO5 IRO9 IRO12 IRO15 IRO19 IRO22 IRO25 IRO29 N.C. N.C. BOOT XEREQ N.C. EA3 EA6 N.C. EA13 ED0 ED4 ED7 Pin no. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 I/O I/O I/O I/O -- I/O I/O I/O I -- O -- I I I I I I -- -- I I I O I O O O O I O O O Pin name ED11 ED14 ICDT14 N.C. ICDT8 ICDT4 ICDT1 INT7 N.C. AINT3 N.C. PSTOP PM F1 MOD1 INT2 XRST N.C. N.C. TCIF SDI0 SCO0 PACK SCO1 PAO2 PAO5 PAO9 PAO12 XICWE PAO16 PAO19 L Pin no. 193 194 195 196 197 198 199 200 201 201 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 I/O O -- -- -- O O -- -- O -- O -- O -- O -- O O -- I/O I/O -- I/O -- I/O -- I/O -- O O -- -- Pin name PAO26 VS N.C. VS IRO7 IRO11 VS N.C. IRO24 VS IRO31 VS PAGE0 VS EA0 VS EA8 EA12 VS ED5 ED9 VS ICDT15 VS ICDT7 VS ICDT0 VS AINT4 SCKOUT VS N.C. Pin no. 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 I/O -- -- -- -- I -- I -- O O -- I O -- O -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pin name N.C. VS N.C. VS SMDT VS SCI0 VS ADBRK PAO1 VS XICOPE ST0 VS PAO18 VS VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD N.C.: Pin not connected 5 MB86330 s EXTERNAL PIN LAYOUT MCLK PM PSTOP 3 L FF BREAK XICWE 2 MOD [2 : 0] WMD [1 : 0] 4 XICOPE ICAD [3 : 0] ICCN 16 F1 F0 XRST SCKOUT BOOT 32 ICDT [15 : 0] XMONI ADBRK IRO [31 : 0] 2 32 BTACT PAGE [1 : 0] 3 PAO [31 : 0] PACK PDXED XERD XEREQ 7 ST [2 : 0] SMDT SMCK SMEN INT [7 : 1] 7 16 16 XEWR ED [15 : 0] EA [15 : 0] 2 AINT [7 : 1] TCIF SY1 [1 : 0] 2 SCZC 2 SCI [1 : 0] SDI [1 : 0] SYO [1 : 0] SCO [1 : 0] 2 2 2 SDO [1 : 0] Other pins VD, VS, N.C. 6 MB86330 s PIN DESCRIPTION Pin no. 114 Pin name Bit MCLK 1 I/O I Active -- Pull up or pull down -- Master clock input MCLK SCKout (Internal system clock) Function 1 machine cycle 173 172 50, 116, 175 PM PSTOP MOD [2:0] 1 1 3 I I I -- H -- Pull up -- Internal master clock input can be selected. 0: MCLK, 1: PLL output PLL operation setup 0: PLL operation, 1: PLL stop Pull down Operating mode MOD2 0 MOD1 0 Other than above MOD0 0 Operating mode Single chip mode Disabled 21, 91 WMD [1:0] 2 I -- Pull down External memory WAIT mode WMD1 0 0 1 1 SMD0 0 1 0 1 Wait cycle 0 cyc 5 cyc 15 cyc 30 cyc Can data be rewritten? No No Yes Yes 174 49 177 222 44 151 89 19, 205 67, 132, 237 F1 F0 XRST SCKOUT SCZC BOOT BTACT PAGE [1:0] ST [2:0] 1 1 1 1 1 1 1 2 3 I I I O I I O O O -- -- L -- H H H -- -- -- -- -- -- Flag input 1 (level sense) Flag input 0 (level sense) Reset input Internal system clock output Pull down Hi-z control over SCKOOUT, POUT and EA [15:0] (SCZC = "L") -- -- -- -- Input for a BOOT mode control signal Output for a BOOT mode status indication signal Output for an external memory/page selection control signal Internal status output (Continued) 7 MB86330 Pin no. 229 55 56 Pin name Bit SMDT SMCK SMEN 1 1 1 I/O I I I Active -- -- H Pull up or pull down -- -- -- Function Serial input data (16 bits) for operating mode (SMODE) setup Serial input clock for operating mode (SMODE) setup Pulse input for operating mode (SMODE) setup Upon completion of setup, a positive pulse is entered. Input for INT7 to INT1 interrupt request signals Output for INT7 to INT1 interrupt acknowl edge signals Used for DC setup. "0": PCM, "1": TCH Used to set serial port 1. Input pins for synchronization signals for serial input port 1/0 Clock input for serial input port 1/0 Data input for serial input port 1/0 Synchronization signal input for serial output port 1/0 Clock input for serial output port 1/0 Data output for serial output port 1/0 PLL status output Output for test Break input for the emulator Input for an emulator write signal Input for an emulator read signal 43, 109 to 111, INT 118, 168, 176 [7:1] 41, 42, 51, 52, AINT 108, 170, 221 [7:1] 180 58, 123 59, 231 124, 181 125, 126 182, 184 60, 61 192 70 115 189 236 2, 6, 10, 79 64 TCIF SYI [1:0] SCI [1:0] SDI [1:0] SYO [1:0] SCO [1:0] SDO [1:0] L FF BREAK XICWE XICOPE ICAD [3:0] ICCN 7 7 1 2 2 2 2 2 2 1 1 1 1 1 4 1 16 I O I I I I I I O O O I I I I I I/O L L H H -- -- H -- -- -- -- L L L -- H -- Pull up -- -- -- -- -- -- -- -- -- -- Pull up Pull up Pull up Pull down Address input for the emulator Pull down Input for an emulator connection signal Pull down I/O for a data bus used to access the emulator 35 to 37,39, ICDT 103 to 107, 163, [15:0] 165 to 167, 215, 217, 219 127 233 XMONI ADBRK 1 1 O O L H -- -- Output for indicating emulator monitor mode status Output for indicating occurrence of an ADBKP register event for the emulator (Continued) 8 MB86330 (Continued) Pin no. Pin name Bit 32 I/O O Active -- Pull up or pull down -- Function Instruction register output for the emulator 4, 5, 7 to 9, IRO 11 to 16, 76 to 78, [31:0] 80 to 83, 85, 140 to 148, 197, 198, 201, 203 1, 3, 62, 63, 65, PAO 66, 68, 69, [31:0] 71 to 75, 128 to 131, 133 to 138, 185 to 188, 190, 191, 193, 234, 239 183 57 20 152 90 29 to 31, 33, 97, 98, 100 to 102, 158 to 162, 212, 213 PACK PDXED XERD XEREQ XEWR ED [15:0] 32 O -- -- Program address output for the emulator 1 1 1 1 1 16 O O O O O I/O -- -- L L L -- -- -- -- -- -- Pull up Output for a PAO fetch clock for the emulator Output for test Output for an ERAM reading signal Output for an ERAM access request signal Output for an ERAM writing signal External data bus I/O pins 22 to 26, 28, EA 92, 94 to 96, [15:0] 154, 155, 157, 207, 209, 210 241 to 256 VD 16 O -- -- Output for the ERAM address -- -- -- -- -- -- -- -- Power supply for the digital circuit (3.3 V, input) GND (input) for the digital circuit 122, 194, 196, VS 199, 202, 204, 206, 208, 211, 214, 216, 218, 220, 223, 226, 228, 230, 232, 235, 238, 240 17, 18, 27, 32, N.C. 34, 38, 40, 45 to 48, 53, 54, 84, 86 to 88, 93, 99, 112, 113, 117,119 to 121, 139, 149, 150, 153, 156, 164, 169, 171, 178, 179, 195, 200, 224, 225, 227 -- -- -- -- Pins not connected 9 MB86330 s HANDLING DEVICES 1. Take Care So that the Maximum Rated Value Is Not Exceeded. (Preventing Latchup) Latchup may occur on CMOS ICs if voltage higher than VD or lower than VS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section "s Electrical Characteristics" is applied between VD and VS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 4. Treatment of Pins Connected to Pull-up/Pull-down Resistors With neither a pull-up resistor nor a pull-down resistor connected, the pin state is determined depending on the input level that reflects an internal resistor. When controlling the pin state, however, connect a pull-up or pulldown resistor. 10 MB86330 s BLOCK DIAGRAM DSP core Controller PC IR1 Interrupt controller IR2 DRF DEC1 DEC2 MODE RPC RPC2 ARAM (Data memory) Y0 Y1 X0 X1 X2 X3 X4 X5 X6 X7 MD TRAM (Table data memory) SP DMAC0 Bus interface DMAC1 DMAC2 DMAC3 LC0 LC1 I/O peripheral circuit Peripheral circuit Clock generator BRAM (Data memory) Adder BP BV Circular addressing Instruction memory Adder Address generator B-bus A-bus Data operation section Input format A1 A0 B1 B0 C2 C1 C0 D2 D1 D0 Output format SFT MAC#0 MAC#1 ALU Barrel shifter ST SFTV Result selection 11 MB86330 s DESCRIPTION OF BLOCK FUNCTIONS * Clock generator (CLOCK Gen.) Generates a clock required for the DSP to control a system clock stop in the waste state and an entire clock stop for sleeping. * Interrupt controller Controls an INT interrupt, an overflow interrupt, and a DMA interrupt. * Controller Generates a program address and decodes an instruction to control the entire DSP . * Address generator Generates an address required for memory access. It supports a circular addressing function to control the DMA access pointer and the stack pointer. * Data operation section Performs data operations such as product addition, arithmetic operations (multiplication, division, addition and subtraction), logic operations, and shift operations. * Bus interface Controls access to the memory space including instruction reading, data memory access and mapped I/O access. * ARAM/BRAM This is a data memory for data operations. A and B use different banks, enabling double transfer without a wait. (ARAM = 4 kwords, BRAM = 4 kwords) * TRAM (Table data memory) Sets table data required for applications. * Instruction memory Sets program data. * Mapped I/O Supports a macro valid for applications Serial I/O: Two serial ports for transmitting CODEC data. One serial input 1 system for setting operating mode (SMODE) 12 MB86330 s MEMORY SPACE * Configuration of the memory space The memory space consists of a data memory space and an instruction memory space. The I/O, ARAM, BRAM, TABLE, and ERAM (external memory) areas are allocated in the data memory space, while the instruction memory is allocated in the program memory space. The I/O, TABLE, ERAM (external memory), ARAM and BRAM areas in the data memory space are, however, assigned a particular data bus. The memory for any two areas can, therefore, be accessed concurrently during one cycle. What memory is accessed is determined automatically by an address value. Addresses allocated for the memories, and their maximum size are determined as follows. Select a memory size to be allocated in this range. * Memory space mode You can select a method for allocating the data memory space and the program memory space by operating mode. Determine operating mode by mode pins (MOD2, MOD1 and MOD0) as follows. MOD2 0 MOD1 0 Other than above MOD0 0 Operating mode Single chip mode Disabled * Memory map for single chip mode The program for single chip mode (MOD2: 0 = "000") is operated by the internal program RAM (which externally downloads a program). Five areas for I/O, ARAM, BRAM, TABLE and ERAM are allocated on the data memory space, with the instruction memory allocated on a program memory space completely different from the data memory space. Although the instruction memory can have an independent address space for 64 kwords, therefore, you cannot access data in the instruction memory using a program. * Single chip mode (MOD2: 0 = "000") Data memory area 0000H I/O area 1000H 4000H ARAM area 2000H BRAM area 3000H TABLE area 7000H 8000H Internal instruction memory for the user 4100H Emulation work area Instruction memory space 0000H ERAM area FFFFH 16 bits FFFFH 16 bits : The hatched area cannot be used by the user. 13 MB86330 s MEMORY MAP FOR BOOT STRAP ERAM Instruction memory 0000H 0000H 1000H 2000H 3000H Data memory I/O area ARAM BRAM PAGE1 - 0 = 10 0000H PAGE1 - 0 = 00 0000H 4000H 3000H Table data 6FFFH 4000H Table RAM Program 7FFFH PAGE1 - 0 = 11 8000H 7FFFH PAGE1 - 0 = 01 8000H 8000H Instruction RAM ERAM ERAM FFFFH FFFFH FFFFH FFFFH The ERAM area is used by the DSP to access the data memory space. Because the ERAM area ranges from 8000H to FFFFH, however, PAGE is created in units of 32 kwords. PAGE is selected automatically. 14 MB86330 s BASIC PIPELINE OPERATION The DSP splits the contents of processing in one cycle to increase the number of pipeline sectors for high-speed operation. For operations using product adders such as product addition and multiplication, and for operations using 40-bit adders such as 40-bit addition, the processing latency is two cycles. Pipeline phase PC DE1 DE2 EX1 EX2 PC: Program fetch cycle DE1: Decode 1st. cycle DE2: Decode 2nd. cycle EX1: Execute 1st. cycle EX2: Execute 2nd. cycle Operation (latency 1) PC dec1 adr dec2 ALU1 Operation (latency 2) PC dec1 adr dec2 ALU2 Transfer (Reg-Reg R/W) PC dec1 adr dec2 adr dec2 R/W Transfer (Mem Read) PC dec1 R dec1: dec2: adr: [adr] ALU: R: W: 1st. decoding 2nd. decoding Address generation Address maintenance Operation Reading Writing Transfer (Mem Write) PC dec1 adr dec2 [adr] W s PRODUCT ADDITION For product addition and multiplication, the latency is two cycles. Because it is provided with a dual product adder (MAC) for alternate processing every cycle, however, the DSP can process n successive product addition (multiplication) steps in (n + 1) cycles. Operation latency 2 MSM (1) MSM (2) MSM (3) MSM (4) MSM (n - 1) MSM (n) (n + 1) cycles 15 MB86330 s REGISTER TABLE Register name A0 A1 AX B0 B1 BX C0 C1 C2 CX D0 D1 D2 DX X0 X1 X2 X3 X4 X5 X6 X7 Y0 Y1 Bit length 16 16 32 16 16 32 16 16 8 40 16 16 8 40 16 16 16 16 16 16 16 16 16 16 Register type Data register Data register Data register Data register Data register Data register Accumulator Accumulator Accumulator (guard register) Accumulator Accumulator Accumulator Accumulator (guard register) Accumulator Address register Address register Address register Address register Address register Address register Address register Address register Address register update register Address register update register Undefined bit 15 Y0 Y1 bit 0 bit 15 X0 X1 X2 X3 X4 X5 X6 X7 bit 0 bit 39 bit 32 bit 31 D2 D1 bit 16 bit 15 D0 bit 0 DX bit 39 bit 32 bit 31 C2 C1 bit 16 bit 15 C0 bit 0 CX bit 31 B1 bit 16 bit 15 B0 bit 0 BX Initial value Undefined bit 31 Register configuration bit 16 bit 15 A1 A0 bit 0 AX Undefined (Continued) 16 MB86330 (Continued) Register name BP BV MD RPC RPC2 DOSTR DOEND LC0 LC1 SFT SFTV ST MODE DRF DMAC0 DMAC1 DMAC2 DMAC3 PC SP Bit length 16 16 16 16 16 16 16 16 16 6 16 16 16 16 16 16 16 16 16 16 Register type Base pointer Circular register Modulo register Repeat counter 1 Repeat counter 2 DO start address register DO end address register Loop counter Loop counter Shift register Shift register Status register Mode register Flag holding register DMA counter DMA counter DMA counter DMA counter Program counter Stack pointer FFFD Undefined Undefined bit 15 PC SP bit 0 bit 15 DMAC0 DMAC1 DMAC2 DMAC3 bit 0 bit 15 bit 15 BP BV MD RPC RPC2 DOSTR DOEND LC0 LC1 bit 0 SFTV bit 15 bit 0 bit 15 ST bit 0 MODE DRF bit 5 bit 0 SFT bit 0 Initial value Undefined Register configuration 00000000B 00000000B 17 MB86330 s REGISTERS * Data registers (A0, A1, B0 and B1) Each of the data registers consists of four words (16 bits). They can be used as four word-length registers (16 bits) and two long-word registers (32 bits) to execute various arithmetic operation instructions, logic operation instructions, and transfer instructions. * Accumulators (C0 to C1, and D0 to D2) The accumulators can be linked as two 40-bit registers (CX and DX) to execute various arithmetic operation instructions, logic operation instructions, and transfer instructions. The 40-bit length registers (CX and DX) can be specified as destinations for product addition instructions. Four 16-bit length accumulators (C0, C1, D0 and D1), and two 8-bit length accumulators (C2 and D2) are supported. * Address registers (X0 to X7) Eight 16-bit address registers are supported. An address register is used to specify an operand address for transfer. Immediate values (1 to -2) or the address update registers (Y0 and Y1) can be used to update address registers. They can also be updated automatically by transfer. * Address update registers (Y0 and Y1) Two 16-bit address update registers are supported. The address update registers are used to update address registers during addressing. * Base pointer (BP) The base pointer consists of 16 bits. The contents of the base pointer plus a 7-bit immediate value are generated as the address value during direct 7-bit length addressing. * Circular register (BV) The circular register, which consists of 16 bits, provides an offset value for circular addressing. * Modulo register (MD) The modulo register, which consists of 16 bits, is used to specify an addressing range for circular addressing. * Repeat counter (RPC) The repeat counter, which consists of 16 bits, is used to specify the number of times the REP/DO instruction is repeated. During execution of the repeat instruction, the repeat counter is decremented by one every repeat operation cycle. * Repeat counter 2 (RPC2) Repeat counter 2, which consists of 16 bits, is used to specify the number of times the REP2 instruction is repeated. During execution of the repeat 2 instruction, repeat counter 2 is decremented by one every repeat operation cycle. * DO address registers (DOSTR and DOEND) These registers maintain a loop start address (DOSTR)/end address (DOEND) for the DO instruction. They can process only PUSH/POP . * Loop counters (LC0 and LC1) Each of the loop counters consists of 16 bits. They store the number of times repetition is made in a specified address range. (Continued) 18 MB86330 (Continued) * Shift register (SFT) The SFT register consists of signed 6 bits. This shift value storage register stores the number of bits shifted during execution of the shift instruction. * Shift register (SFTV) The SFTV register, which consists of 16 bits, is used to store the results of CMLT and CMGT instruction. * Status register (ST) The status register, which consists of 16 bits, is assigned bits for storing information about results of operations (carry and overflow) and for setting operating mode. * Mode register (MODE) This register is used to specify modes of operations and transfer, and interrupts. * Flag holding register (DRF) This register holds flags for the DO, REP and REP2 instructions. It can process only PUSH/POP This register . is cleared by the PUSH instruction. * DMA counters (DMAC0 to DMAC3) When a DMA interrupt occurs, this register stores the address of the data transfer source or the data transfer destination. * Program counter (PC) The program counter, which consists of 16 bits, points to the memory address that stores an instruction code to be executed by the CPU. While it is updated automatically by instruction execution, the program counter can be rewritten by a conditional branch, a subroutine call instruction, an interrupt, and a reset. Executing the repeat instruction stops a program counter update. * Stack pointer (SP) The stack pointer, which consists of 16 bits, stores addresses for saving and transferring the contents of registers upon execution of the PUSH/POP instruction, the subroutine call instruction, or an interrupt. 19 MB86330 s DETAILED DESCRIPTION OF SPECIAL REGISTERS (1) Status Register bit 15 IT bit 14 OV3 bit 13 OV1 bit 12 INT2 bit 11 INT1 bit 10 bit 9 bit 8 CP bit 7 RND bit 6 ITG bit 5 V3 bit 4 V2 bit 3 V1 bit 2 N bit 1 Z bit 0 C INT0 MDMA Bit abbreviation C Bit name Carry flag Description Set when carry occurs as a result of operation execution. Reset when no carry occurs. Not changed by transfer instruction execution. Set when the operation result is 0. Reset when the operation result is not 0. Not changed by transfer instruction execution. Set when the operation result is smaller than 0. Reset when the operation result is equal to or greater than 0. Not changed by transfer instruction execution. Set when the operation result overflows. Reset when the operation result does not overflow. Not changed by transfer instruction execution. Set when the operation result overflows. Set V2 is reset only by hardware or by ST programming by the transfer instruction. Not changed by transfer instruction execution. Set when the operation result of an instruction stored in CX or DX cannot be expressed by 32 bits (but by 40 bits). Reset when the operation result can be expressed by 32 bits. Specify this when executing multiplication in integral mode. Used to set ON/OFF of rounding processing when data is transferred from a register consisting of 32 or more bits to a 16-bit register. Used to specify whether the operation result is to be clipped when overflow occurs during the operation. Enables a DMA interrupt. (0: Disabled) INT0 (SMODE) interrupt enable flag 0: Disabled, 1: Enabled INT1 interrupt enable flag 0: Disabled, 1: Enabled INT2 interrupt enable flag 0: Disabled, 1: Enabled Operation overflow interrupt enable flag. An interrupt is generated when V1 is set. 0: An interrupt is disabled. 1: An interrupt is enabled. Operation overflow interrupt enable flag. An interrupt is generated when V3 is set. 0: An interrupt is disabled. 1: An interrupt is enabled. OV1, OV3 and INT0 to INT7 interrupt enable flag 0: An interrupt is disabled. 1: An interrupt is enabled. Z Zero flag N Negative flag V1 Overflow flag 1 V2 Overflow flag 2 V3 Overflow flag 3 ITG RND Operating mode specification flag Rounding mode setup CP MDMA INT0 INT1 INT2 OV1 Clip flag DMA enable flag Interrupt enable flag Interrupt enable flag Interrupt enable flag V1 interrupt enable flag OV3 V3 interrupt enable flag IT 20 Interrupt enable flag MB86330 (2) Mode Register bit 7 INT7 bit 6 INT6 bit 5 INT5 bit 4 INT4 bit 3 INT3 bit 2 -- bit 1 NCT bit 0 NOG Bit abbreviation NOG Bit name Operating mode specification 0: Ordinary mode The guard bit is used. 1: NOG mode No guard bit is used. Description NCT -- INT3 INT4 INT5 INT6 INT7 Transferred data clipping specification Indeterminate Interrupt enable flag Interrupt enable flag Interrupt enable flag Interrupt enable flag Interrupt enable flag 0: Transferred data is clipped. 1: Transferred data is not clipped. Reserved INT3 interrupt enable flag 0: Disabled, 1: Enabled INT4 interrupt enable flag 0: Disabled, 1: Enabled INT5 interrupt enable flag 0: Disabled, 1: Enabled INT6 interrupt enable flag 0: Disabled, 1: Enabled INT7 interrupt enable flag 0: Disabled, 1: Enabled 21 MB86330 (3) DRF Register bit 7 REPF23 bit 6 REPF22 bit 5 REPF21 bit 4 REPF13 bit 3 REPF12 bit 2 REPF11 bit 1 DOF1 bit 0 DOF2 Bit abbreviation DOF2 DOF1 REPF11 REPF12 REPF13 REPF21 REPF22 REPF23 Bit name DO flag 2 DO flag 1 REP1 flag 1 REP1 flag 2 REP1 flag 3 REP2 flag 1 REP2 flag 2 REP2 flag 3 Description Internal operation status holding flag. Only PUSH and POP are available. Cleared by the PUSH instruction. 22 MB86330 s ADDRESSING * Types of addressing When reading/writing data from/to the memory, you can use a direct addressing method for specifying a 16-bit length address space with an immediate value, and an indirect addressing method for referencing that space by an address register. The DSP supports eight address registers, two update registers, the base pointer, the circular register, and the modulo register for addressing. * Addressing classification Three indirect addressing means (AD0 to AD2) by address registers can be used to transfer a register value to a memory, data from a memory to a register, and data between memories. The available addressing means is determined depending on the type of a register for data transfer, double transfer and transfer accompanied by an operation. All addressing is performed in units of words. 23 MB86330 * Addressing modes Mode Mnemonic Direct addressing AD0 (imm16) (Xk + + 1) (Xk + + 0) (Xk - - 1) (Xk + + Y0) (Xm + + 3) (Xm + + 2) (Xm + + 1) (Xm + + 0) (Xm - - 1) (Xm - - 2) (Xm - - 3) (Xm + + Y1) [BV+X7 + + 3] [BV+X7 + + 2] [BV+X7 + + 1] [BV+X7 + + 0] [BV+X7 - - 1] [BV+X7 - - 2] [BV+X7 - - 3] [BV+X7 + + Y1] AD2 (BP+disp7) (Xn + + 2) (Xn + + 1) (Xn + + 0) (Xn - - 1) (Xn - - 2) (Xn - - 3) (Xn + + Y0) (Xn + + Y1) [BV+Xn + + 2] [BV+Xn + + 1] [BV+Xn + + 0] [BV+Xn - - 1] [BV+Xn - - 2] [BV+Xn - - 3] [BV+Xn + + Y0] [BV+Xn + + Y1] Effective address imm16 Xk Xk Xk Xk Xm Xm Xm Xm Xm Xm Xm Xm BV+X7 BV+X7 BV+X7 BV+X7 BV+X7 BV+X7 BV+X7 BV+X7 BP+disp7 Xn Xn Xn Xn Xn Xn Xn Xn BV+Xn BV+Xn BV+Xn BV+Xn BV+Xn BV+Xn BV+Xn BV+Xn Register update Not updated +1 Not updated -1 Y0 +3 +2 +1 Not updated -1 -2 -3 Y1 +3 +2 +1 Not updated -1 -2 -3 Y1 Not updated +2 +1 Not updated -1 -2 -3 Y0 Y1 +2 +1 Not updated -1 -2 -3 Y0 Y1 Description 16-bit direct addressing Xk can be assigned X0, X1, X2 and X3. AD1 Xm can be assigned X4, X5 and X6. Indirect addressing For circular addressing, only X7 can be used. Xn can be assigned X0, X1, X2, X3, X4, X5, X6 and X7. disp7 is signed 7 bits. [ ] : Indicates circular addressing. AD0 : For "AD0," you cannot specify circular addressing. AD1 : For "AD1," circular addressing mode is set automatically when "X7" is selected as the address register. With "0" set in the "MD" and "BV" registers, the same operation as ordinary addressing is performed even if "X7" is selected as the address register. AD2 : disp7 in "AD2" is signed 7 bits. 24 MB86330 s BASIC CONFIGURATION OF THE DATA OPERATION SECTION 1. Data Format Integral type and fixed-point data can be handled regardless of whether the data is signed or unsigned. For signed data, the most significant bit indicates a sign. A number of 1 indicates negative data, which is expressed by 2's complement. The decimal point for fixed-point type data is located between the sign bit (bit 14) and its right bit (bit 15). When the accumulator value resulting from execution of a multiplication instruction is transferred to a 16-bit length register or memory, the decimal point is returned to the original position (between bits 14 and 15). * Fixed-point type, signed data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit S Decimal part (2's complement) Sign Decimal point * Fixed-point type, unsigned data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit Decimal part Decimal point * Integral-type, signed data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit S Integral part (2's complement) Sign * Integral-type, unsigned data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit Integral part Since a value is handled in 2's complement format for addition and subtraction, no distinction is made in the result of an operation by the above four data format. Since, for multiplication, the result of an operation varies with whether data is signed or unsigned, three combinations of "signed data x signed data," "signed data x unsigned data," and "unsigned data x unsigned data" exist for multiplication instructions. For the fixed-point type and the integral type, the result of multiplication varies with the decimal point position. When fixed-point type data is multiplied, the result of the operation is stored into the accumulator with one bit shifted to the left in comparison with integral type data. The "ITG" bit in the status register is used to switch between the fixed-point type and the integral type. With this bit set at 0, an operation is executed in the fixedpoint type format. 25 MB86330 2. Multiplication in Fixed-point Type Mode With the "ITG" bit in the status register set at 0, fixed-point type mode is set up, and multiplication is executed in the following format. You can use ordinary mode and NOG mode in which the guard bit is not used. (1) Ordinary Mode * Fixed-point type multiplication (signed data x signed data) 31 bits of the result of a signed operation are stored into bits 1 to 31 in the accumulator shifted to the left by one bit. "0" is set to bit 0, with the same value as at bit 31 set to bits 32 to 39. 15 14 13 12 1 0 16 bits S x S 0 16 bits S S S S 17 16 15 14 31 bits of an operation result 2 1 0 0 40 bits 39 38 32 31 30 29 28 Sign extension * Fixed-point type multiplication (signed data x unsigned data) 32 bits of the result of a signed operation are stored into bits 1 to 32 in the accumulator shifted to the left by one bit. "0" is set to bit 0, with the same value as at bit 32 set to bits 33 to 39. 15 14 13 12 1 0 16 bits S x S 39 0 16 bits S S 17 16 15 14 32 bits of an operation result 2 1 0 0 40 bits 33 32 31 30 29 28 Sign extension * Fixed-point type multiplication (unsigned data x unsigned data) 32 bits of the result of an unsigned operation are stored into bits 1 to 32 in the accumulator shifted to the left by one bit. "0" is set to bit 0, and bits 33 to 39. 15 14 13 12 1 0 16 bits x 0 16 bits 0 39 0 33 32 31 30 29 28 0 is set. 17 16 15 14 32 bits of an operation result 2 1 0 0 40 bits 26 MB86330 (2) NOG Mode In this mode, the CX and DX registers are handled as a 32-bit accumulator in which detected overflow is clipped. * Fixed-point type multiplication (signed data x signed data) 31 bits of the result of a signed operation are stored into bits 1 to 31 in the accumulator shifted to the left by one bit. "0" is set at bit 0. 15 14 13 12 1 0 16 bits S x S S 31 30 29 28 17 16 15 14 31 bits of an operation result 2 1 0 0 0 16 bits 32 bits 27 MB86330 s INTERRUPT A software interrupt and a hardware interrupt are available. Interrupts are assigned specified types of priority. When interrupts occur concurrently, an interrupt with higher priority is executed earlier. Priority 1 2 Soft/hard Hard Hard Soft 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Hard Soft Interrupt type RST BREAK TRAP V1 V3 DMA0 DMA1 DMA2 DMA3 INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 0XFFFC 0XFFFA -- -- -- -- 0XFFF8 0XFFF6 0XFFF4 0XFFF2 0XFFF0 0XFFEE 0XFFEC 0XFFEA Interrupt branch destination 0XFFFE 0X0002* Cause of an interrupt Hardware reset External reset signal input Setup of emulator operation mode External break signal input Setup of emulator operation mode Software (TRAP instruction) Occurrence of arithmetic operation overflow (V1) Occurrence of arithmetic operation overflow (V3) DMA0 signal input (for data input) DMA1 signal input (for data input) DMA2 signal input (for data output) DMA3 signal input (for data output) SDOME interrupt signal input External interrupt signal input (INT1) External interrupt signal input (INT2) External interrupt signal input (INT3) External interrupt signal input (INT4) External interrupt signal input (INT5) External interrupt signal input (INT6) External interrupt signal input (INT7) * : Memory space for a debug instruction Notes: * Emulator operation mode is set by a hardware interrupt resulting from external break signal input and by a software interrupt by the TRAP instruction. * Any interrupts other than a reset are disabled during downloading. 28 MB86330 s INSTRUCTIONS Mnemonic ABS ADD ADD ADDC ADSB ADX AND Operation overview Absolute value calculation Addition Addition with transfer Addition with carry Addition and subtraction Address register addition Logical AND Logical AND .... MSB C 0 Shift with transfer .... MSB C MSB C Conditional relative branch Subroutine jump Transfer with (major) comparison conditions Transfer with (minor) comparison conditions Comparison Block repetition Division support Conditional absolute branch Conditional absolute branch Absolute branch .... C 0 0 .... C A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX RPC/imm 10 AX, BX, CX, DX/A0, A1, B0, B1, C0, C1, D0, D1 .... A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX Acc S1 + A1 reg (AD1) A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX A0, A1, B0, B1 Xn Xn + Immediate value A0, A1, B0, B1, C0, C1, D0, D1 ST 0 A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX CX, DX reg (AD1) Flag change N 0 Z C - V1 V2 - - - - - - - - - - V3 - - - - - 29 - - - - - - - - - - - - - - - - - ASL ASL ASR BRCC CALL CMGT CMLT CMP DO DSTP JPC0 JPC1 JUMP LSL LSR A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX - - - - - - - - - - - - - - - - - - - - - - (Continued) MB86330 Mnemonic MOV Operation overview Data transfer or duplicate transfer Inter-register transfer REG REG Transfer between a memory and a register MEM REG Duplicate transfer B0 (AD0), A1 (AD1) B0 (AD0), B1 (AD1) Immediate value transfer to a register REG Immediate value Inter-memory transfer (AD0) (AD1) CX, DX (AD1) A0, A1,B0, B1/CX, DX acc acc - A0 x A1 A0 (AD0), A1 (AD1) acc acc - B0 x B1 B0 (AD0), B1 (AD1) A0, A1, B0, B1/CX, DX A0, A1, B0, B1/CX, DX A0, A1, B0, B1/CX, DX acc acc + A0 x A1 A0 (AD0), A1 (AD1) acc acc + B0 x B1 B0 (AD0), B1 (AD1) acc acc + (A0 or A1) x A1 reg (AD1) A0, A1, B0, B1/CX, DX acc acc + A0 x A1 A0 (AD0), A1 (AD1) acc acc + B0 x B1 B0 (AD0), B1 (AD1) A0, A1, B0, B1/CX, DX acc acc + A0 x A1 A0 (AD0), A1 (AD1) acc acc + B0 x B1 B0 (AD0), B1 (AD1) Flag change N - Z - C - V1 - V2 - V3 - MOVT MRD MRD Duplicate transfer to the accumulator Signed product addition Signed product addition with duplicate transfer - - - 0 0 - - - - - - - - - 0 0 0 0 0 0 0 0 0 MSMU Unsigned and unsigned product addition with duplicate transfer MSMU Unsigned and unsigned product addition MSMS Signed and unsigned product addition with duplicate transfer MSMS Signed and unsigned product addition MSM Signed product addition with transfer MSM Signed product addition with duplicate transfer MSM Signed product addition MRDU Unsigned and unsigned product addition MRDS Signed and unsigned product addition (Continued) 30 MB86330 Mnemonic MUL MUL Operation overview Signed multiplication Signed multiplication with duplicate transfer A0, A1, B0, B1, C0, C1, D0, D1/CX, DX acc A0 x A1 A0 (AD0), A1 (AD1) acc B0 x B1 B0 (AD0), B1 (AD1) acc (A0 or A1) x A1 reg (AD1) A0, A1, B0, B1, C0, C1, D0, D1/CX, DX acc A0 x A1 A0 (AD0), A1 (AD1) acc B0 x B1 B0 (AD0), B1 (AD1) A0, A1, B0, B1, C0, C1, D0, D1/CX, DX acc A0 x A1 A0 (AD0), A1 (AD1) acc B0 x B1 B0 (AD0), B1 (AD1) Inter-register transfer REG REG A0, A1, B0, B1, C0, C1, D0, D1 A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX A0, A1, B0, B1, C0, C1, D0, D1 ST Flag change N Z C - - V1 - - V2 - - V3 - - - - - - - - - 31 - - - - - - MUL MULS MULS Signed multiplication with transfer Signed and unsigned multiplication Signed and unsigned multiplication with duplicate transfer Signed and unsigned multiplication Signed and unsigned multiplication with duplicate transfer Conditional transfer Logical NOT 2's complement operation None executed Logical OR - - - - - - - - - MULU MULU - - - - - - MVCC NOT NEG NOP OR - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - POP PUSH REGU REP REP2 RET RET1 Return of a register from the stack Saving of a register to the stack Auxiliary normalization operation Repeated execution of the subsequent instruction Repeated execution of the subsequent instruction Return from a subroutine Return from an interrupt routine CX, DX RPC/imm 10 RPC2/imm 10 - - - - - (Continued) MB86330 (Continued) Mnemonic RGLT RVL SLP STLD Operation overview Auxiliary search for the minimum normalized value Reverse shift Standby status Store and load (AD0) A0, A0 (AD1) (AD0) A1, A1 (AD1) (AD0) CX, CX (AD1) (AD0) DX, DX (AD1) A0, A1, B0, B1 A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX acc acc - A1 reg (AD1) A0, A1, B0, B1, C0, C1, D0, D1, AX, BX, CX, DX A0, A1, B0, B1, C0, C1, D0, D1 CX, DX A0, A1, B0, B1, C0, C1, D0, D1 Flag change N - Z C - V1 - - - - V2 - - - - V3 - - - - - - - - - - SBAD SUB SUB SUBC XOR Subtraction and addition Subtraction Subtraction with transfer Subtraction with carry Exclusive logical OR - - - - [Flag indications] : Set or reset by an operation : Not changed or reset by an operation - : Not changed by an operation : Not changed or reset by an operation 0 : Reset by an operation 32 - MB86330 s BOOT 1. BOOT Mode BOOT mode supports the following functions. * Ordinary BOOT function (Booting the instruction RAM (48 kwords)/the table RAM (16 kwords)) * Simplified BOOT function (Booting some instruction RAMs) 2. Setting BOOT Mode Only single chip mode is available. (1) Command Setup Load the ERAM area (FFE0H to FFE3H: PAGE1-0 = 11) with the following contents during booting. * Address FFE0: Command contents 0001H to 000BH : Reserved 000CH : Simplified booting 000DH to 0010H : Reserved Others : Ordinary booting * Address FFE1: Start address Specify the start address of a program to be booted during simplified booting. * Address FFE2: Size Specify the program size of a program to be booted during simplified booting. * Address FFE3: Execution start address Specify an execution start address after completion of simplified booting. (2) Ordinary BOOT function (Command = other than 0001H to 0010H) The ordinary BOOT function loads a full-word program (48 kwords) and table data (16 kwords), then moves execution to the user program (jump to address FFFE) or ICE (jump to address 0002). (3) Simplified BOOT function (Command = 000CH) The Simplified BOOT function loads and executes a program of 48 k or fewer words. It also sets loaded start address (FFE1H), the number of program words (FFE2H), and execution start address (FFE3H). 33 MB86330 3. BOOT Timing Performing BOOT processing requires satisfaction of the following operation. (1) Take setup of two or more MCLK clocks from a fall rising edge. (2) Fetch information about the BOOT pin at a fall rising edge, and the BTACT pin will be set at "H". (3) Reset the BOOT pin at least two MCLK clocks after a fall edge observed at the BTACT pin. (4) When the BTACT pin is changed from "H" to "L", BOOT operation is terminated. * PM = 0 (When PLL is not used) XRST MCLK [RESET] SCKOUT BOOT BTACT (1) (2) (3) * PM = 1 (When PLL is used) XRST MCLK [PLL-clk] [RESET] SCKOUT BOOT BTACT (1) (2) (3) 34 MB86330 s PLL 1. PLL operation Performing this DSP operation using PLL requires satisfaction of the following operation. When using PLL, set the PSTOP pin at "H" for 1 sec or more for a reset, then at "L", and wait for lockup time or more time. (1) Take enough time for MCLK input and for lockup at the PLL operation state with PSTOP equal to "L". (2) Hold the DSP reset state until PLL is locked. (XRST = "L") (3) When PLL is locked, the "L" pin goes "H". (4) After PLL has been locked, change XRST from "L" to "H" to start DSP operation. VDD MCLK PSTOP lock up time L XRST Initial time ( s) 2. PLL standards Input clock (MHz) 20 to 25 Look up time (s) 200 Remarks When PLL is used 35 MB86330 s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = 0 V) Parameter Power supply voltage Input voltage Output voltage Maximum output current Storage temperature Symbol VDD VI VO IO IO Tstg Condition VDD - VSS -- -- VO = VDD VO = 0 V -- Value Min. VSS - 0.5 VSS - 0.5 VSS - 0.5 -- -- -65 Max. 4.0 VDD + 0.5 VDD + 0.5 14 -14 +150 Unit V V V mA mA Remarks Input pin Output pin BUS pin Output drive pin (IOL) 4 mA Ceramic package C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 2. Recommended Operating Conditions (VSS = 0 V) Parameter Power supply voltage "H" level input voltage "L" level output voltage Ambient temperature Symbol VDD VIH VIL TA Value Min. 3.0 0.65 VDD VSS 0 Typ. 3.3 -- -- -- Max. 3.6 VDD + 0.3 0.25 VDD +40 Unit V V V VDD Remarks C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 36 MB86330 3. Operating Frequency Operating Frequency TA = +40C 110 Frequency [MHz] 105 100 95 90 3.0 3.3 Power supply voltage [V] 3.6 4. DC Characteristics (VDD = 3.0 to 3.6 V, VSS = 0 V, TA = 0C to +40C) Parameter Symbol IDDS Condition Standby mode*1 Ordinary operation mode -- -- IOH = -4mA IOL = 4mA VI = 0 - VDD -- State Normal/IOL = 4 mA Value Min. -- -- 0.65 VDD VSS VDD - 0.5 VSS -5 -5 25 VO = VDD +60 Typ. 50 62 -- -- -- -- -- -- 50 -- -- Max. -- -- VDD 0.25 VSS VDD 0.4 5 5 200 VO = 0 V -60 Unit A mA V V V V A A k mA mA Power supply voltage "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input leakage current*2 (Tri-state pin) Pull-up/pull-down resistor Output current (Shorting circuit) IDD VIH VIL VOH VOL ILI ILZ RP IO*3 *1: The memory is set at the standby state with VIH = V DD and VIL = VSS. *2: With the input pin provided with a pull-up or pull-down resistor, the standard value may be exceeded. *3: Maximum supply current at the output section, and the VDD or VSS circuit 37 MB86330 5. AC Characteristics (1) ERAM Interface SCKOUT tDEA EA [15 : 0] tHEA tFREQ XEREQ tDRD tWRD XERD tWWR XEWR tRREQ tDWR in ED [15 : 0] valid tSDRD tHDRD out valid tDDWR tHDWR Note: During a wait, the state indicated by double lines above is held for a wait cycle. (VDD = 3.0 V to 3.6 V, TA = 0C to +40C, output pin load = 50 pF) Parameter EA output delay EA hold time XEREQ falling delay XEREQ rising delay XERD rising delay XERD "L" pulse width XEWR rising delay XEWR "L" pulse width ED setup time for XERD ED hold time for XERD ED delay time for XEWR ED hold time for XEWR Symbol tDEA tHEA tFREQ tRREQ tDRD tWRD tDWR tWWR tSDRD (in) tHDRD (in) tDDWR (out) tHDWR (out) Pin name EA EA XEREQ XEREQ XERD XERD XEWR XEWR ED ED ED ED Value Min. -- 2.6 -- -- -- 5.8 -- 4.2 10.3 1.5 -- 0.3 Typ. -- -- -- -- -- -- -- -- -- -- -- -- Max. 6.2 -- 5.5 4.2 1.0 -- 2.5 -- -- -- 8.5 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 38 MB86330 (2) Serial I/O Interface * Serial input tCYCSCI SCI0/1 SYI0/1 tHSYI tSSYI tSSYI SDI0/1 Valid Valid tHSDI tSSDI Valid * Serial output tCYCSCO SCO0/1 SYO0/1 tHSYO tSSYO tSSYO SDO0/1 Valid tDSDO Valid Valid 39 MB86330 (VDD = 3.0 V to 3.6 V, TA = 0C to +40C, output pin load = 50 pF) Parameter Serial input clock cycle SYI signal setup time SYI signal hold time SDI signal setup time SDI signal hold time Serial output clock cycle SYO signal setup time SYO signal hold time SDO signal output delay Symbol tCYCSCI tSSTI tHSYI tSSDI tHSDI tCYCSCO tSSYO tHSYO tDSDO Pin name SCI [1 : 0] SYI [1 : 0] SYI [1 : 0] SDI [1 : 0] SDI [1 : 0] SCO [1 : 0] SYO [1 : 0] SYO [1 : 0] SDO[1 : 0] Value Min. Typ. 500 2.1 1.4 1.5 2.0 -- -- -- -- 500 2.2 1.4 -- -- -- -- -- -- 5.6 -- -- -- Max. Unit ns ns ns ns ns ns ns ns ns 40 MB86330 (3) SMODE SMDT SMCK SMEN MSB 14 13 2 1 LSB tCYCSMCK SMCK tSSMENlh tHSMENlh tSSMENhl tHSMENhl SMEN SMDT tSSMDT Valid Valid Valid tHSMDT (VDD = 3.0 V to 3.6 V, TA = 0C to +40C, output pin load = 50 pF) Parameter Serial input clock cycle SMDT SMCK setup time SMDT SMCK hold time SMEN SMCK setup time SMEN SMCK hold time SMEN SMCK setup time SMEN SMCK hold time Symbol tCYCSMCK tSSMDT tHSMDT tSSMENhl tHSMENhl tSSMENlh tHSMENlh Pin name SMCK SMDT SMDT SMEN SMEN SMEN SMEN Value Min. Typ. 500 0.8 1.8 0.6 0.6 0.6 0.8 -- -- -- -- -- -- -- -- -- -- -- -- Max. Unit ns ns ns ns ns ns ns 41 MB86330 (4) PLL and Others SCKOUT tDST ST [2 : 0] Valid tHST tDPAGE PAGE [1 : 0] Valid tHPAGE SCZC tDEASC EA [15 : 0] tHEASC tDSCKSC SCKOUT tHSCKSC (VDD = 3.0 V to 3.6 V, TA = 0C to +40C) Parameter ST output delay ST hold time PAGE output delay PAGE hold time EA output delay for SCZC EA hold time for SCZC EA output delay for SCZC EA hold time for SCZC Symbol tDST tHST tDPAGE tHPAGE tDEASC tHEASC tDSCKSC tHSCKSC Pin name ST [2 : 0] ST [2 : 0] PAGE [1 : 0] PAGE [1 : 0] EA [15 : 0] EA [15 : 0] SCKOUT SCKOUT Value Min. -- 0.8 -- 1.3 -- 2.2 -- 1.1 Typ. -- -- -- -- -- -- -- -- Max. 3.3 -- 5.3 -- 5.4 -- 3.2 -- Unit ns ns ns ns ns ns ns ns 42 MB86330 (5) MCLK, XRST MCLK tCYC XRST tPWRST (VDD = 3.0 V to 3.6 V, TA = 0C to +40C) Parameter MCLK cycle (when PLL is used) MCLK cycle (when PLL is not used) Symbol fCYC fCYC Pin name MCLK MCLK Value Min. 20 -- Typ. -- -- Max. 25 160 Unit MHz MHz Remarks * * * : Input the MCLK cycle value so that the MCLK duty-cycle becomes 50% 5%. Value Min. 10tCYC* Typ. -- Max. -- Parameter XRST "L" pulse width * : tCYC = 1/fCYC Symbol tPWRST Pin name XRST Unit ns 43 MB86330 s ORDERING INFORMATION Part number MB86330CR-ES Package 256-pin Ceramic PGA (PGA-256C-A03) Remarks 44 MB86330 s PACKAGE DIMENSIONS 256-pin Ceramic PGA (PGA-256C-A03) C1.02 (.040) TYP (4PLCS) 0.13 0.46 + 0.05 - DIA .005 (.018 + .002 ) - 2.54 (.100) MAX 1.27 (.050) DIA TYP (4PLCS) 45.72 (1.800) REF INDEX AREA 50.04 0.51 SQ (1.970 .020) 1.27 + 0.25 - 0.76 + .010 - .030 2.54 0.25 (.100 .010) 3.30 (.130 + 0.51 - 0.25 + .020 - .010 EXTRA INDEX PIN (.050 ) 6.35 (.250) MAX ) (c) 1994 FUJITSU LIMITED R256003SC-3-2 Dimensions in mm (inches) 45 MB86330 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9810 (c) FUJITSU LIMITED Printed in Japan 46 |
Price & Availability of MB86330
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